DK-DEV-5SGXEA7N【PDF 82/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-12

RCLK Control Block

SV51005

2014.01.10

When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1 ), or a

combination of clock pins or PLL outputs.

Figure 4-11: GCLK Control Block for Stratix V Devices

CLKp

Pins

The CLKn pin is not a dedicated

clock input when used as a

single-ended PLL clock input. The

When the device is in user mode,

you can dynamically control the

PLL Counter

Outputs

CLKSELECT[1..0]

2

2

2

CLKn

Pin

Internal

Logic

CLKn pin can drive the PLL using

the GCLK.

clock select signals through

internal logic.

Static Clock

When the device is in user mode, you can

This multiplexer

supports user-controllable

dynamic switching

Enable/

Disable

Select

only set the clock select signals through a

configuration file (SRAM object file [ .sof ] or

programmer object file [ .pof ]) because the

signals cannot be controlled dynamically.

Internal

GCLK

Logic

RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit

settings in the configuration file ( .sof or .pof ) generated by the Quartus II software.

Figure 4-12: RCLK Control Block for Stratix V Devices

The CLKn pin is not a dedicated

clock input when used as a

CLKp

Pin

CLKn

Pin

single-ended PLL clock input. The

CLKn pin can drive the PLL using

PLL Counter

Outputs

2

Internal Logic

Static Clock Select

the RCLK.

When the device is in user mode,

you can only set the clock select

Enable/

Disable

signals through a configuration file

( .sof or .pof ); they cannot be

controlled dynamically.

Internal

Logic

RCLK

You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers

through the Quartus II software using the ALTCLKCTRL megafunction.

Note: When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the

inputs using the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1]

ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.

Related Information

Clock Control Block (ALTCLKCTRL) Megafunction User Guide

Provides more information about ALTCLKCTRL megafunction.

Altera Corporation

Clock Networks and PLLs in Stratix V Devices

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